Microelectronic elements often comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a semiconductor wafer. A wafer can be formed to include multiple integrated chips or dies on a surface of the wafer and/or partly embedded within the wafer. Dies that are separated from a wafer are commonly provided as individual, prepackaged units. In some package designs, the die is mounted to a substrate or a chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board (PCB). For example, many dies are provided in packages suitable for surface mounting.
Packaged semiconductor dies can also be provided in “stacked” arrangements, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow a number of different dies to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between the packages. Often, this interconnect distance can be only slightly larger than the thickness of the die itself. For interconnection to be achieved within a stack of die packages, interconnection structures for mechanical and electrical connection may be provided on both sides (e.g., faces) of each die package (except for the topmost package).
Additionally, dies or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking a layer of one or more dies on a larger base die, stacking multiple dies in a vertical arrangement, and various combinations of both. Dies may also be stacked on wafers or wafers may be stacked on other wafers prior to singulation. The dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct bonding, non-adhesive techniques such as a ZiBond® technique or a hybrid bonding technique, also known as DBI®, both available from Invensas Bonding Technologies, an Xperi company (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety).
There can be a variety of challenges to implementing stacked die and wafer arrangements. For example, as IC chip technology matures, smaller packages are possible due to smaller and denser ICs. Finer pitch interconnects are a natural result of finer pitch design rules, and are also desirable to connect smaller chip packages and components to each other and to other carriers, PCBs, and the like. Fine pitch interconnects can be tightly arranged on a die surface (e.g., 1-10 um), however, making access to a particular interconnect by a test probe or a programming probe (e.g., 20-40 um) difficult. For instance, the size of the probe compared to the pitch and density of the fine pitch interconnects can cause multiple interconnects to be shorted while accessing a single pad. Further, it can be possible to damage a small pad while probing it for testing or programming.
This is particularly true in the case of true three dimensional packaging, where the signal pitch can be much finer than what can be practically probed. Interconnect size and pitch on the dies can be significantly reduced and interconnect density can be greatly increased with direct bonding techniques. Thus, the neighborhood of a test pin could be too crowded to fit a larger pad on the die surface. Additionally, with hybrid bonding a.k.a. DBI®, the topology induced by a probe may make the surface incapable of bonding. Surface topologies within nanometer range are generally required for this hybrid bond, and the scrub of a probe can cause surface topology disruptions, sometimes much greater than several nanometers.